1. Field of the Invention
The present invention relates to a semiconductor device consisting of P-channel and N-channel thin-film transistors arranged on the same substrate and also to a method of fabricating such a semiconductor device. More particularly, the invention relates to a CMOS circuit configuration composed of thin-film transistors formed on a glass substrate and also to a method of fabricating this CMOS circuit configuration.
2. Description of the Related Art
A technique for fabricating a thin-film transistor (TFT) by growing a thin film of silicon on a glass substrate is known. This technique has been developed to fabricate active matrix liquid crystal displays.
A liquid crystal display comprises a pair of glass substrates together with a liquid crystal material held between the substrates. A large number of pixels are arranged in rows and columns. For each pixel, an electric field is applied across the liquid crystal material to vary its optical property. Thus, an image is displayed.
In the active matrix liquid crystal display, a TFT is disposed at each of the pixels arranged in rows and columns as described above. This TFT controls electric charge going into and out of the pixel electrode.
In the present technology, a peripheral driver circuit for driving hundreds of TFTs X hundreds of TFTs arranged in the active matrix region is composed of an IC circuit (known as a driver IC) attached to the outside of a glass substrate by TAB (tape automated bonding) or other technique.
However, mounting driver IC to the outside of the glass substrate complicates the manufacturing process. Also, the driver IC results in unevenness. This hinders wide application of the liquid crystal display incorporated in various electronic appliances.
A technique for solving these problems consists of fabricating the peripheral driver circuit out of TFTs and integrating these TFTs with other TFTs on the glass substrate. This makes the whole system a unit.
Furthermore, the process sequence is simplified, the reliability is enhanced, and the application can be extended.
In this active matrix liquid crystal display incorporating the peripheral driver circuit as described above, CMOS circuits are necessary to form the peripheral driver circuit. A CMOS circuit is a complementary combination of an N-channel transistor and a P-channel transistor, and is one of fundamental configurations of electronic circuits. The following various methods for fabricating CMOS configuration out of TFTs on a glass substrate are known.
One known method is illustrated in FIGS. 4(A)-4(D). As shown in FIG. 4(A), a silicon oxide film 402 acting as a buffer layer is first formed on a glass substrate 401. An active layer, 403 and 404, made of crystalline or amorphous silicon is formed on the silicon oxide film 402. A silicon oxide film 405 serving as a gate-insulating film is coated on the laminate. The active layer portion 403 is an island of region forming an active layer for an N-channel TFT. The active layer portion 404 is an island of region forming an active layer for a P-channel TFT.
After obtaining the state shown in FIG. 4(A), gate electrodes 406 and 407 are fabricated out of silicide or other material (FIG. 4(B)).
Then, as shown in FIG. 4(C), phosphorus (P) ions are implanted while masking the other TFT region with a resist mask 408. As a result, a source region 409, a drain region 411, and a channel formation region 410 for the N-channel TFT are formed by self-aligned technology.
Thereafter, as shown in FIG. 4(D), the resist mask 408 is removed. A new resist mask 412 is placed. At this time, boron (B) ions are implanted. By this manufacturing step, a source region 415, a drain region 413, and a channel formation region 414 for the P-channel TFT are formed by self-aligned technology.
In this way, the N-channel and P-channel TFTs can be formed simultaneously on the same glass substrate. In the configuration shown in FIGS. 4(A)-4(D), the drain region 411 of the P-channel TFT is connected with the drain region 413 of the N-channel TFT. The gate electrodes of both TFTs are connected together. Consequently, a CMOS configuration is obtained.
The manufacturing steps shown in FIGS. 4(A)-4(D) are the most fundamental processes for CMOS circuits. However, two separate masks 408 and 412 used for implantation of dopant ions for imparting N-type conductivity and P-type conductivity, respectively, are necessary. This complicates the process sequence. That is, the two resist masks 408 and 412 are necessitated during the dopant ion implantation.
In order to form each resist mask, a resist material must be applied, sintered, selectively exposed, using a photomask, and selectively removed for formation of the resist mask. Furthermore, where dopant ions are implanted, using a resist as a mask, the resulting ion bombardment modifies the quality of the resist. This makes it difficult to remove the resist mask.
Where the manufacturing steps illustrated in FIGS. 4(A)-4(D) are adopted, it follows that two manufacturing steps for removing the resist material which has been modified in quality and thus is difficult to remove are performed. This will be another factor of defects. Hence, these two steps are undesirable.
A known method of alleviating this problem is illustrated in FIGS. 5(A)-5(D). As shown in FIG. 5(A), a silicon oxide film 502 is formed as a buffer layer on the glass substrate 401. An active layer, 503 and 504, of crystalline or amorphous silicon is formed on the silicon oxide film 502. A silicon oxide film 505 acting as a gate-insulating film is formed over the laminate. The active layer portions 503 and 504 are islands of regions forming active layers for N- and P-channel TFTs, respectively. Then, gate electrodes 506 and 507 of silicide or other material are formed, thus giving rise to a state shown in FIG. 5(B).
Under this condition, phosphorus (P) ions are implanted into the whole surface. As a result, N-type regions 508, 510, 511, and 513 are formed (FIG. 5(C)). The dose of the P ions is 1×1015 to 2×1015 ions/cm2. The surface dose is 1×1020 ions/cm2 or more.
Then, a resist mask 514 is placed only on selected regions forming an N-channel TFT. Boron (B) ions are implanted at a dose about 3 to 5 times as high as the dose of the aforementioned P ions. The N-type regions 511 and 513 are converted into P-type. In this way, P-channel source region 515, drain region 516, and channel formation region 512 are formed by self-aligned technology.
The heavy doping described above is required because it is necessary that the regions 515, 512, and 516 form an NIN junction. In this manner, N- and P-channel TFTs can be obtained with a fewer number of masks than the configuration shown in FIG. 4(A)-4(D). In the configuration shown in FIGS. 5(A)-5(D), the N-channel TFT has the source region 508, channel formation region 509, and drain region 510. The P-channel TFT has the drain region 516, channel formation region 512, and drain region 515. Although the configuration shown in FIGS. 5(A)-5(D) has the advantage that it can be manufactured with simplified manufacturing steps, the configuration has the following drawbacks.
First, dopant ions are implanted into the resist mask 514 at a quite high dose. This gives rise to a conspicuous modification of the quality of the resist. This in turn often results in defective manufacturing steps.
Secondly, the right TFT (P-channel TFT) as viewed in FIGS. 5(A)-5(D) has the channel formation region. The drain region adjacent to this channel formation region is a quite heavily doped region. The dose is in excess of the dose necessary for the P-channel type and sufficient for type-conversion. Therefore, the off current near the junction between the channel formation region and the drain region is negligible.
Thirdly, ions take unstraight paths, thus introducing B ions into the channel formation region 512. As a consequence, required characteristics cannot be obtained.
Fourthly, implanting dopant ions at a high dose imposes heavy burden on the ion implanter and on the plasma implant machine. Also, much labor is required to decontaminate the inside of the machine and to service the machine. In this way, various problems take place.
Fifthly, introducing dopant ions at a high dose increases the processing time.
Sixthly, where annealing is carried out with laser light, difficulties occur. After the step shown in FIG. 5(D), the resist mask 514 is removed. Then, an annealing step for activating the implanted dopants and annealing the doped regions with laser irradiation is necessary. This method is useful where a glass substrate having poor heatproofness is used. At this time, the regions 515 and 516 are more severely deteriorated in crystallinity than the regions 508 and 510, because the regions 516 and 516 are more heavily doped than the regions 508 and 510. Therefore, the regions 508 and 510 differ greatly from the regions 515 and 516 in dependence of light absorption coefficient on wavelength. Under this condition, the annealing effect of the laser irradiation differs materially between these two kinds of regions. Consequently, the left N-channel TFT and right P-channel TFT have greatly different characteristics with undesirable results.